ESSDERC 2015 Workshop “Variability – from Equipment to Circuit Level”

Graz, September 18, 2015

Welcome and orientation
J. Lorenz, Fraunhofer IISB

Variability at all levels – a challenge for the semiconductor industry
A. Juge, ST

Overview of the SUPERTHEME project
J. Lorenz, Fraunhofer IISB

Defects responsible for BTI in CMOS devices: MORDRED perspective
A. Shluger, UCL

Variability-aware process simulation in SUPERTHEME
E. Bär, Fraunhofer IISB

Variability-aware device simulation in SUPERTHEME
S. Amoroso / A. Asenov, GU/GSS

Hierarchical modeling of reliability and time-dependent variability in the MORV project
B. Kaczer, IMEC

Covering variability from unit process up to circuit level for mixed-signal circuits
R. Minixhofer, ams

Variability-aware SPICE modeling and circuit simulation in SUPERTHEME
C. Millar, GSS